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Send a note to be added to the waitlist ASAP

​​​

​3G Shielding Specialties

ACDi

Adiva Corporation

​Aerotek

Alan Lupton Associates

Altium

American Circuits

​Antenna Test Lab

Arrow Electronics

​Aspocomp Group

Assembly Technology

​Aurora Technical Sales

Bare Board Group

Better Boards​

C&C Technologies

Cadence Design Systems

Carolina Electronic Assemblers

Circuit Technology

Compunetics

​Creation Technologies

DNA Group

​Downstream Technologies

​Elantas PDG

Electronic Interconnect

​Eltek USA

EMA

​EMA Design Automation

Emerging Power

ERNI Electronics

Fineline - USA

Firan Technology Group (FTG)​

Gardner & Meredith

General Microcircuits

GRT Electronics

​Isola Group

​I-TECH eServices

​IMDS DATA

Indium Corporation

IPC

​JBC Tools USA

​JMC Too & Machine

Keysight Technologies

Leader Tech

Lincoln Technology Solutions

Marathon Technical Assoc

Mentor, a Siemens Business

METZ Connect USA

Nelson-Miller

​Oasis Scientific

PalPilot

​Panacol-USA

​Performance Technical Sales

PFC Flexible Circuits Limited

PICA Manufacturing Solutions

Porticos

Porticos Asia Limited

​Printed Circuit Design & Fab

​Protolabs

​Pulsonix

​Rep Inc

​Risho

Royal Circuit Solutions

​Samtec

​SEP Co

​Tektronix

​Teledyne LeCroy

​TFS, Inc.

The Test Connection

​Touchstone 3D

​TriMech

​TTM Technologies

Wallace Electronic Sales

WDL Systems

Wurth Electronics CBT

Zentech Manufacturing


2018 Exhibitor List

Tel:  (919) 342-0810​

Session 3D  (3:30 - 4:30, Room 3)

Routing-Complex-Interfaces-Utilizing-Intelligent-Design-Planning-Techniques.pdf


Speaker: Mike Catrambone, Cadence


Title: Routing Complex Interfaces Utilizing Intelligent Design Planning Techniques


Abstract: Intelligent planning plays a critical role through all stages of the design process. 
Looking at interfaces from a hierarchical level while fine tuning and optimizing
connections lowers your risk of unexpected rip-ups at the wrong time late in a project. 
This paper will talk about the design challenges encountered by PCB designers today and
how careful planning of these complex routing interfaces can accelerate routing and
tuning signals by as much as 75%.  The paper also provides techniques that designers
can apply to breakout sequencing, point to-point routing, and tuning of signals


Bio: Michael Catrambone is a Sr. Principal Product Engineer for Allegro PCB products at Cadence Design Systems, focusing on Allegro Core Functionality (Constraint Management, High Speed Interfaces & Interconnect and Emerging Technologies).  Mike joined Cadence in 2012 as a Principal Product Validation Engineer prior to moving into his current role in 2015. Prior to joining Cadence he had over twenty four years’ experience in PCB development, Library Management, EDA software support and value-added process improvement working for such companies as Automated Systems, US Robotics, 3Com Corporation, CommWorks, UTStarcom and Plexus Engineering Solutions.  He is deeply involved with the Cadence user community, a Past Chairman of CDNLive - Cadence User Group and a Past Board Member of the International Cadence Users Group.