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​3G Shielding Specialties

ACDi

Adiva Corporation

​Aerotek

Alan Lupton Associates

Altium

American Circuits

​Antenna Test Lab

Arrow Electronics

​Aspocomp Group

Assembly Technology

​Aurora Technical Sales

Bare Board Group

Better Boards​

C&C Technologies

Cadence Design Systems

Carolina Electronic Assemblers

Circuit Technology

Compunetics

​Creation Technologies

DNA Group

​Downstream Technologies

​Elantas PDG

Electronic Interconnect

​Eltek USA

EMA

​EMA Design Automation

Emerging Power

ERNI Electronics

Fineline - USA

Firan Technology Group (FTG)​

Gardner & Meredith

General Microcircuits

GRT Electronics

​Isola Group

​I-TECH eServices

​IMDS DATA

Indium Corporation

IPC

​JBC Tools USA

​JMC Too & Machine

Keysight Technologies

Leader Tech

Lincoln Technology Solutions

Marathon Technical Assoc

Mentor, a Siemens Business

METZ Connect USA

Nelson-Miller

​Oasis Scientific

PalPilot

​Panacol-USA

​Performance Technical Sales

PFC Flexible Circuits Limited

PICA Manufacturing Solutions

Porticos

Porticos Asia Limited

​Printed Circuit Design & Fab

​Protolabs

​Pulsonix

​Rep Inc

​Risho

Royal Circuit Solutions

​Samtec

​SEP Co

​Tektronix

​Teledyne LeCroy

​TFS, Inc.

The Test Connection

​Touchstone 3D

​TriMech

​TTM Technologies

Wallace Electronic Sales

WDL Systems

Wurth Electronics CBT

Zentech Manufacturing


2018 Exhibitor List

Tel:  (919) 342-0810​

Session 4A  (9:30 - 10:30, Room 4)

Improve-SMT-Assembly-Yields-Using-Root-Cause-Analysis-in-Stencil-Design.pdf


Speaker: Greg Smith, Blue Ring Stencils


Title: Improve SMT Assembly Yields Using Root Cause Analysis in Stencil Design


Abstract: Reduction of first pass defects in the SMT assembly process minimizes cost, assembly time and improves reliability.  These three areas, cost, delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process.   It’s commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process.  As form factor continues to get smaller, the challenge to obtain 100% yield becomes more difficult.   This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause.   Outer layer copper weight and surface treatment will also be addressed as to their effect on printability.  Experiments using leadless and emerging components will be studied and root cause analysis will be presented on the following common SMT defects: 
• Poor Solder Paste Release:  Focus will be placed on small components
• Solder-balls (Mid Chip Solder Beads): Stencil design to minimize solderballs
• Tombstoning: Improving tombstoning with stencil design
• Bridging at Print: Simple guidelines to eliminate bridging
• Insufficient Solder Volume at SMT Reflow: Look at the correlation of stencil design to solder volume after reflow
• Bridging at SMT Reflow: What causes bridging after reflow when it is not present after print
• Voiding:  Design ideas to reduce voiding through stencil design
This paper summarizes the results of this study with respect to the variables tested.  Root Causes of these challenges will be identified and practical stencil design recommendations will be made with the intent of eliminating defects and improving yields during the printing process.  


Bio: Greg Smith is the manager of Stencil Technology at BlueRing Stencils. He was the owner and President of a stencil manufacturing company for 23 years prior to joining FineLine Stencil and has worked in the electronics industry since 1989. Since the merger of FineLine and MET, he is new the Manager of Stencil Technology for BlueRing Stencils where he works with customers on stencil design and performs root cause analysis to improve customer yields. He has published and presented many papers at industry events and has been in the SMT Stencil industry for 28 years.