Session 4B (11:00 - 12:00, Room 4)
Speaker: Mike Catrambone, Cadence
Title: Shorten Time to Design Your PCBs by Identifying DFx Issues Earlier in the Design
Abstract: Preventing design defects that reduce manufacturing yield is everyone’s business. An ideal way to improve your design schedule is to eliminate change requests from your PCB fabricator by identifying issues and fixing your design before handoff. This paper will show an approach of detecting DfX issues early and how this can eliminate unnecessary iterations for fixing issues. It will show how PCB designers can easily identify insufficient spacing between objects, wrong pad/ring sizes, threats of acid traps, missing mask elements, etc. Making sense of the results expedites the process of finding and correcting errors at the source. Come share your experiences with the group with what steps your team took to improve your designs’ manufacturability before handoff.
Bio: Michael Catrambone is a Sr. Principal Product Engineer for Allegro PCB products at Cadence Design Systems, focusing on Allegro Core Functionality (Constraint Management, High Speed Interfaces & Interconnect and Emerging Technologies). Mike joined Cadence in 2012 as a Principal Product Validation Engineer prior to moving into his current role in 2015. Prior to joining Cadence he had over twenty four years’ experience in PCB development, Library Management, EDA software support and value-added process improvement working for such companies as Automated Systems, US Robotics, 3Com Corporation, CommWorks, UTStarcom and Plexus Engineering Solutions. He is deeply involved with the Cadence user community, a Past Chairman of CDNLive - Cadence User Group and a Past Board Member of the International Cadence Users Group.