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​3G Shielding Specialties

ACDi

Adiva Corporation

​Aerotek

Alan Lupton Associates

Altium

American Circuits

​Antenna Test Lab

Arrow Electronics

​Aspocomp Group

Assembly Technology

​Aurora Technical Sales

Bare Board Group

Better Boards​

C&C Technologies

Cadence Design Systems

Carolina Electronic Assemblers

Circuit Technology

Compunetics

​Creation Technologies

DNA Group

​Downstream Technologies

​Elantas PDG

Electronic Interconnect

​Eltek USA

EMA

​EMA Design Automation

Emerging Power

ERNI Electronics

Fineline - USA

Firan Technology Group (FTG)​

Gardner & Meredith

General Microcircuits

GRT Electronics

​Isola Group

​I-TECH eServices

​IMDS DATA

Indium Corporation

IPC

​JBC Tools USA

​JMC Too & Machine

Keysight Technologies

Leader Tech

Lincoln Technology Solutions

Marathon Technical Assoc

Mentor, a Siemens Business

METZ Connect USA

Nelson-Miller

​Oasis Scientific

PalPilot

​Panacol-USA

​Performance Technical Sales

PFC Flexible Circuits Limited

PICA Manufacturing Solutions

Porticos

Porticos Asia Limited

​Printed Circuit Design & Fab

​Protolabs

​Pulsonix

​Rep Inc

​Risho

Royal Circuit Solutions

​Samtec

​SEP Co

​Tektronix

​Teledyne LeCroy

​TFS, Inc.

The Test Connection

​Touchstone 3D

​TriMech

​TTM Technologies

Wallace Electronic Sales

WDL Systems

Wurth Electronics CBT

Zentech Manufacturing


2018 Exhibitor List

Tel:  (919) 342-0810​

Session 4B  (11:00 - 12:00, Room 4)

Shorten-Time-to-Design-Your-PCBs-by-Identifying-DFx-Issues-Earlier-in-the-Design-Cycle.pdf


Speaker: Mike Catrambone, Cadence


Title:  Shorten Time to Design Your PCBs by Identifying DFx Issues Earlier in the Design


Abstract: Preventing design defects that reduce manufacturing yield is everyone’s business.  An ideal way to improve your design schedule is to eliminate change requests from your PCB fabricator by identifying issues and fixing your design before handoff.  This paper will show an approach of detecting DfX issues early and how this can eliminate unnecessary iterations for fixing issues. It will show how PCB designers can easily identify insufficient spacing between objects, wrong pad/ring sizes, threats of acid traps, missing mask elements, etc.  Making sense of the results expedites the process of finding and correcting errors at the source.  Come share your experiences with the group with what steps your team took to improve your designs’ manufacturability before handoff.


Bio: Michael Catrambone is a Sr. Principal Product Engineer for Allegro PCB products at Cadence Design Systems, focusing on Allegro Core Functionality (Constraint Management, High Speed Interfaces & Interconnect and Emerging Technologies).  Mike joined Cadence in 2012 as a Principal Product Validation Engineer prior to moving into his current role in 2015. Prior to joining Cadence he had over twenty four years’ experience in PCB development, Library Management, EDA software support and value-added process improvement working for such companies as Automated Systems, US Robotics, 3Com Corporation, CommWorks, UTStarcom and Plexus Engineering Solutions.  He is deeply involved with the Cadence user community, a Past Chairman of CDNLive - Cadence User Group and a Past Board Member of the International Cadence Users Group.