Session 6A (9:30 - 10:30, Room 6)
Speaker: Jay Diepenbrock, Independent Signal Integrity Consultant
Title: Design Challenges at 56 Gb/s and Beyond
Abstract: All the buzz in the electronics design world seems to be about 56 Gb/s and even 112 Gb/s, like it’s just another turn of the design cycle. However, if one digs a little deeper, one finds that it’s not that easy. The same design constraints are still in play – loss budgets, crosstalk, impedance discontinuities, and power integrity, but they’re getting harder to meet. New effects that were not big factors at 10 and 28 Gb/s are now significant enough that they can no longer be ignored. This presentation will discuss some of those effects and their causes, and some of the techniques being used to understand and mitigate them at 56 Gb/s and beyond.
Bio: Joseph C. (Jay) Diepenbrock holds an Sc. B. (EE) from Brown University and an MSEE from Syracuse University. He worked in a number of development areas in IBM including IC, analog and RF circuit, and backplane design. He then moved to IBM’s Integrated Supply Chain, working on the electrical specification, testing, and modeling of connectors and cables and was IBM’s Subject Matter Expert on high speed cables. After a long career at IBM he left there and joined Lorom America as Senior Vice President, High Speed Engineering, and led the Lorom Signal Integrity team, supporting its high speed product development. He left Lorom in 2015, and is now an independent signal integrity consultant. Mr. Diepenbrock has authored or co-authored a number of technical papers, and contributed to a number of industry standards, is a Senior Member of the IEEE, and holds 12 patents. In his spare time, he enjoys amateur radio, playing jazz music, making furniture, photography, and volunteer and church work, with particular interest in disaster relief.